Frequency dividers, such as divide-by-two frequency dividers, receive a clock input at one frequency and deliver an output signal at half the frequency of the clock input. Frequency dividers are used in such applications as phase-locked loops (PLL), sensors, and electronic watches. Typical applications focus on designing the frequency dividers to maximize speed or minimize power consumption. Optimization of frequency dividers for speed or power consumption typically results in complex circuits with numerous electronic components. However, such circuits sacrifice the phase noise performance in order to obtain higher operating speeds and lower power consumption.
An improved frequency divider circuit is desirable.